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Summary The human neocortex exhibits characteristic regional patterning (arealization) critical for higher-order cognitive function. Disrupted arealization is strongly implicated in neurodevelopmental disorders (NDDs), but current neocortical organoid models largely fail to recapitulate this patterning, limiting mechanistic understanding. Here, we establish a straightforward method for generating arealized organoids through short-term early exposure to anterior (FGF8) or posterior (BMP4/CHIR-99021) morphogens. These treatments created distinct anterior and posterior signaling centers, supporting long-lasting polarization, which we validated with single-cell RNA sequencing that revealed area-specific molecular signatures matching prenatal human cortex. To demonstrate the utility of this platform, we modeled Fragile X Syndrome (FXS) in organoids with distinct anterior and posterior regional identities. FXS organoids showed highly disrupted SOX4/SOX11 expression gradients along the anterior-posterior axis, consistent with alterations found in autism spectrum disorder (ASD) and demonstrate how regional patterning defects may contribute to NDD pathology. Together, our study provides a robust platform for generating neocortical organoids with anterior-posterior molecular signatures and highlights the importance of modeling NDDs using experimental platforms with neuroanatomic specificity. 

In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computing a convolutional neural network (CNN) model [1]. Recent works investigated the use of analog-mixed-signal (AMS) hardware for high area and energy efficiency [2], [3]. However, AMS hardware output is well known to be susceptible to process, voltage, and temperature (PVT) variations, limiting the computing precision and ultimately the inference accuracy of a CNN. We reconfirmed, through the simulation of a capacitor-based IMC SRAM macro that computes a 256D binary dot product, that the AMS computing hardware has a significant root-mean-square error (RMSE) of 22.5% across the worst-case voltage, temperature (Fig. 16.1.1 top left) and 3-sigma process variations (Fig. 16.1.1 top right). On the other hand, we can implement an IMC SRAM macro using robust digital logic [4], which can virtually eliminate the variability issue (Fig. 16.1.1 top). However, digital circuits require more devices than AMS counterparts (e.g., 28 transistors for a mirror full adder [FA]). As a result, a recent digital IMC SRAM shows a lower area efficiency of 6368F2/b (22nm, 4b/4b weight/activation) [5] than the AMS counterpart (1170F2/b, 65nm, 1b/1b) [3]. In light of this, we aim to adopt approximate arithmetic hardware to improve area and power efficiency and present two digital IMC macros (DIMC) with different levels of approximation (Fig. 16.1.1 bottom left). Also, we propose an approximation-aware training algorithm and a number format to minimize inference accuracy degradation induced by approximate hardware (Fig. 16.1.1 bottom right). We prototyped a 28nm test chip: for a 1b/1b CNN model for CIFAR-10 and across 0.5-to-1.1V supply, the DIMC with double-approximate hardware (DIMC-D) achieves 2569F2/b, 932-2219TOPS/W, 475-20032GOPS, and 86.96% accuracy, while for a 4b/1b CNN model, the DIMC with the single-approximate hardware (DIMC-S) achieves 3814F2/b, 458-990TOPS/W